There is demand for integrated circuits that are smaller and capable of performing more functions than conventional integrated circuits. Thus, to increase circuit density, manufacturers continue to decrease process feature sizes of integrated circuits dramatically, such as from 0.13 um to 90 nm and even 65 nm. The resultant increase in circuit density on a die increases a density of in/out ports that couple signals and power on and off of the die. In other words, the number of in/out ports in a given die area increases.
The in/out ports on the die are coupled via an integrated circuit package, such as a conventional fine-pitch flip-chip ball grid array (BGA) with a conventional interposer, to a circuit external to the integrated circuit package, such as a circuit on a printed circuit board. The conventional fine-pitch flip-chip BGA has multiple conductive and dielectric layers which form multiple redistribution layers (RDLs). An RDL relocates an in/out port contact. The fine-pitch flip-chip BGA has an expensive manufacturing process due to the many steps required to manufacture a multi-layer device. The fine-pitch flip-chip BGA also has poor thermal performance due to the thermally insulative effect of multiple RDLs. Thus, as the density of in/out ports increases, the number of RDLs and manufacturing costs increase with a consummate reduction in thermal performance.
The in/out ports on the die may also be coupled via a common quad flat non-leaded package (QFM). The QFM package requires a conventional leadframe insulated from the die with a dielectric layer and having leads placed beyond a perimeter of the die. Thus, terminals coupling in/out ports of the die cannot be located between the die and the leadframe. This limits the in/out port density of the QFM.
As the density of in/out ports on the die increases, conventional wafer-level chip scale packages (CSP) for a small die, such as those listed above, must be capable of coupling an increased density of in/out ports. However, the conventional CSP do not accommodate an in/out port density that is high enough. Thus, as the process feature size becomes smaller, conventional CSPs do not accommodate commensurate increases in the density of in/out ports.
Therefore, what is needed is an improved semiconductor package and manufacturing process that overcomes the shortcomings described above.